Electronic devices, such as computers, modems, facsimile machines, and mobile devices, often include memory devices to store data. As technological advances increase memory capacity and memory chip density, smaller geometries are used to manufacture memory cells. However, smaller geometries may cause memory failure rates to increase. A memory failure may result in incorrect data being transmitted in response to a memory request. Thus, increasing error protection at a memory is useful.
One way to improve error protection is to include an Error Checking and Correcting (ECC) module in a memory device to check for errors and correct detected errors at the memory device. However, an ECC process may add significant latency (e.g., time corresponding to the ECC checking and correcting data before it is transmitted) to a memory request at the memory device. Further, an amount of additional latency may depend on whether an error is present (e.g., a variable latency memory device), which may be unknown before the memory request is transmitted to the memory device. Modern memory interfaces (e.g., dynamic random-access memory (DRAM) interfaces) may use a fixed latency signal transmission system. In a fixed latency signal transmission system, a controller may need to know when to expect a response to a memory request. A fixed latency signal transmission system that includes the variable latency memory device may need to ensure that the variable latency memory device will always return data with a worst-case latency (e.g., a latency that corresponds to the ECC module finding and correcting an error) to ensure that the variable latency memory device will always transmit data with a fixed latency. However, assuming that the variable latency memory device will always return data at the worst-case latency may negatively impact a performance associated with the memory device.